The invention relates to the design of semiconductor devices and checking that the designs meet certain criteria (ground rules).
Field effect transistors (FETs) are fabricated using Complementary Metal-Oxide Semiconductor (CMOS) techniques. Most commercial silicon semiconductor processes create transistors by the implantation of dopants into a bulk silicon wafer. For example, in an “N-Well” process, the N-FETs are formed in the bulk material (or in a twin P-well in the P-substrate) and the P-FETs transistors are formed in an “N-Well” which is implanted into the substrate. An N-Well is an example of what will be referred to herein as a “conductor region”.
A problem inherent in the fabrication of CMOS transistors is “latch up”, also known as the “thyristor effect”. Generally, adjacent P-FETs and N-FETs create lateral, parasitic, bipolar structures (e.g., thyristors, SCRs, transistors) which, under certain conditions, can produce functional failure due to excessive drain current. One way by which the latch up can be avoided is by providing N-well and P-well contacts (also known as “well contacts”, “substrate ties”, “substrate contacts” and “butting contacts”) in close proximity to all active elements (junctions) of the FETs to keep leakage currents small.
Design Rule Checking (DRC) is performed on an integrated circuit (IC) chip design to ensure that the design meets various criteria (ground rules). For example, a latch up check can be performed to determine whether a design meets the criteria of having well contacts in close proximity (e.g., within 20 μm) to the active elements (i.e., the FET junctions).
FIG. 1 is a block diagram illustrating a simplified exemplary architecture of an IC design system 100 within which the present invention can be embodied. Design information is stored in a hardware (H/W) description/representation file 102 and can be read by a design representation reader 104 capable of processing the design information. Design rules may be included in a control file associated with the hardware design representation 102, such as a control file 106. The system 100 also includes a control file reader 108. The system 100 includes a model builder 110, a design analyzer 112, a property manager 114, an analysis engine 116, and a report manager 118. The model builder 110 receives output of the hardware design representation reader and the control file reader 108 and builds an internal representation of the hardware design, i.e., a model. The design analyzer 112 automatically produces a comprehensive set of attributes such as design verification checks based upon a predetermined set of properties. The property manager 114 maintains information regarding relationships among the checks generated by the design analyzer 112 and additionally maintains information regarding relationships among properties and whether the properties are satisfied, violated, or whether the results are indeterminate or conditional upon one or more other properties. The property manger 114 and the analysis engine 116 may cooperate to determine dependency relationships among a comprehensive set of design verification checks. The analysis engine 116 verifies the model produced by the model builder 110 by testing for violations of the properties. The analysis engine 116 may employ an analysis-based technique, such as an integration of simulation and formal analysis methodologies, so as to maximize stimulus coverage for the design under test. Alternatively, simulation, functional verification, or other well-known verification methodologies may be employed individually. The report manager 118 provides feedback to the designer, in the form of a report file 120, for example, regarding potential design defects. Results are maintained in a results database 122. Conventional Input/Output (I/O) devices have been omitted, for illustrative clarity.
Semiconductor devices are designed using tools (e.g., layout editor) which generate geometric patterns (shapes) representing the various elements of the semiconductor device for example, the conductive regions and well contacts discussed above. The shapes generated by the layout editor are typically generated as “vector images” using a vector graphics program. A layout tool may be embodied in the design system 100.
Vector images comprise mathematically-defined geometric shapes (scalable objects)—lines, curves, shapes, objects and fills. These scalable objects are defined by mathematical equations. Since vectors entail both magnitude and direction, vector elements are thus comprised of line segments whose length represents magnitude and whose orientation in space represents direction. Vector graphic images are readily scaled. In contrast with vector images, “raster images” (also known as “bitmap images”) comprise a plurality of picture elements (pixels) which are typically arranged in a grid, such as an array of rows and columns. As relevant to the present invention, each cell of a raster image array can be filled with a byte (digital value).
FIGS. 2A and 2B illustrate a generalized situation wherein latch up may occur, as described hereinabove. An exemplary conductor region 202 (such as an N-well) is shown. The conductor region 202 can be any arbitrary shaped polygon, and can contain several active devices and any number of contacts, such as well 204. The well contact 204 is disposed within the conductor region 202. In this example, the conductor region 202 is a U-shaped polygon having two “legs”, a left-hand (as viewed) leg and a right-hand (as viewed) leg. In this example, the well contact 204 has a square shape and is disposed near the end of the left-hand leg of the U-shaped conductor region 202.
The U-shaped conductor region 202 is termed a “non-convex” polygon. A polygon is defined to be “convex” if for any two points that lie within the polygon, a line segment connecting them is also inside the polygon. A regular octagon (e.g., shape of a traffic stop sign) is an example of a convex polygon. For simplicity, a “concave” polygon is defined as any polygon which is not “convex”. The U-shaped conductor region 202 is a concave polygon. It is not a convex polygon.
A distance “I” is defined as the minimum required separation of the outside edges of the conductor shape, and is illustrated as the size of a gap between the two legs of the U-shaped polygon in the conductor region. This distance “I” is also used as an expansion increment, as discussed below, and is generally the largest expansion increment that will work, although it may be advantageous to choose a smaller value (for expansion) in some circumstances.
The location of the well contact 204 within the conductor region 202, and the overall size of the conductor region 202 are important, for the following reason. Any part of the conductor region 202 which is farther than a distance “D” from the well contact 204 is defined as “unreachable”. This is illustrated by the arrow 206. In this example, a portion 208 (shown cross hatched in FIG. 2A) of the conductor region 202 is unreachable (by the contact 204)—namely, an upper end portion of the right-hand leg of the U-shaped conductor region 202. By definition, the remaining portion 210 of the conductor region 202 is “reachable”. In this example, the reachable portion (area) 210 of the conductor region 202 comprises the left-hand leg (including the contact area) and the bottom of the U-shaped conductor region 202, as well as a lower portion of the right-hand leg of the U-shaped conductor region 202.
FIG. 2B also shows three junctions 212, 214, 216 superimposed on the conductor region 202. The junction 212 is within the reachable area 210, the junction 214 is partially within the reachable area 210 and partially within the unreachable area 208, and the junction 216 is entirely within the unreachable area 208. Any junctions touching the unreachable area 208 are defined as “erroneous”, and corrective measures are required (e.g., to avoid latch up). In this example, the junctions 214 and 216 are erroneous. The junction 212 is not erroneous. The corrective measures may simply involve placing additional contacts within the conductor region. In layman's terms, any transistor junctions which are formed in conductive regions should be within a distance “D” of a well contact. Otherwise, problems may occur. This is all well known.
FIGS. 3-9 illustrate an exemplary situation wherein latch up may occur, as described hereinabove. Two well contacts 304 and 306 (compare 204) are disposed within a conductor region 302 (compare 202). As in the previous example, the conductor region 302 is a U-shaped polygon having two “legs”, a left-hand (as viewed) leg and a right-hand (as viewed) leg, and is not convex.
The contact 304 has a rectangular shape and is disposed in a lower-left corner portion of the conductor region 302. The contact 306 has a square shape and is disposed in a lower-right corner portion of the conductor region 302. The contacts 304 and 306 are shown as being disposed inward from the perimeter of the conductor region 302, but they can also be disposed against the perimeter of the conductor region 302.
A traditional method of determining the reachable area (e.g., 210) of a conductor region (e.g., 202) involves iteratively expanding the contact shapes and intersecting them with the conductor region shape until the conductor region is completely filled, or until the distance limit (“D”) has been reached. The method proceeds as follows.
First, the contact shapes 304 and 306 are expanded (enlarged) by the expansion increment (I). The expansion increment “I” is defined as the minimum required separation of the outside edges of the conductor region shape. As mentioned above, the distance “I” is defined as the minimum required separation of the outside edges of the conductor shape, and is illustrated as the size of a gap between the two legs of the U-shaped polygon of the conductor region. This distance “I” is also used as an expansion increment, and is generally the largest expansion increment that will work, although it may be advantageous to choose a smaller value (for expansion) in some circumstances. The increment “I” is, by definition, less than “D”, and “D” can be defined as a multiple of “I” (D=n*I). (There may be a remainder to D/I, i.e. D=n*I+R) For example, “I”=approximately 1 μm and “D”=approximately 50-100 μm. The expanded contact shapes (new contact areas) are shown as 404 and 406, respectively, in FIG. 4. (Getting a little ahead of ourselves, and as described below, by expanding the contact shapes up to “n” times, the expanded contact shapes will represent the reachable area of the conductor region.) The contact shapes 304 and 306 are vector graphic images, and are readily scaled (expanded) simply by specifying a larger size for the image.
As is evident in FIG. 4, portions of the expanded contact shapes 404 and 406 can extend to outside of the conductor region 302. Therefore, any portion of the new contact area 404 and 406 which falls outside the conductor region shape 302 is trimmed (cropped, deleted). The cropped contact shapes 504 and 506 are shown in FIG. 5. Their outer edges are coincident with the outer edges of the conductor shape 302.
This cropping step is important because: (i) the conductor region shape 302 is non-convex; and therefore, (ii) a contact shape (e.g., 304) that is being expanded could (in a few or several expansion steps) expand to outside of the conductor region shape could re-enter the conductor shape. (For example, a contact could expand outside of one leg of the U-shaped conductor region and then, in a next expansion step, enter the other leg of the U-shaped conductor region in an area which is not reachable via the conductor region.)
A check is performed to see if the new (expanded) contact shapes (504, 506) completely fill the conductor region shape. If so, stop—the entire conductor region 302 is reachable. In other words, if the contact shapes have been expanded less than n times, and the expanded contact shapes fill the conductor area, the entire conductor region is reachable. Otherwise, as in this example where the first expansion did not fill the entire conductor region, the expanded contact areas 504 and 506 are expanded again, by increment “I”, and cropped (if necessary, as in this example). The resulting (twice expanded) contact shapes 604 and 606 are shown in FIG. 6.
The process of expanding and cropping continues, up to a maximum of “n” times (the maximum cumulative expansion amount), and at each expansion step there is a determination of whether the conductive region 302 has been filled.
If the maximum cumulative expansion amount has not been attained (fewer than n expansions have occurred), and the conductive shape 302 is filled, then the entire conductor region 304 is “reachable”.
If the maximum cumulative expansion amount (“n” expansions) has been attained, and the conductive shape 302 is not filled, then part (a portion) of the conductive region is not reachable. Such a situation is shown in FIG. 7. The expanded contact shapes 704 and 706 do not completely fill the conductive shape 302. Rather, two areas 708 and 712 (shown cross hatched in FIG. 7, compare 208) of the conductive shape 302 are not reachable, and any junctions located in those non-reachable areas are considered to be “erroneous”. In this case, the total area 708 and 712, representing the area of the conductive region shape 302 remaining after exhausting the maximum cumulative expansion amount, is readily computed by performing a geometric “difference” operation, i.e., subtracting the expanded contact shapes 704, 706 from the conductive region shape 302. As shown in FIG. 8, these remaining areas 708 and 712 (compare 208) are unreachable. The areas 810a and 810b (compare 210) are “reachable”. The shapes 708 and 712 representing the unreachable areas of the conductor region 302 are then checked against junction shapes in the design and any junction shapes which intersect the unreachable areas are flagged as errors.
A typical distance for “D” is 50-100 μm. A typical distance for “I” is 1 μm. D=n*I (+R), wherein “n” is the number of expansions performed to explore reachability. Typically, a few tens (e.g., 20, 30) of expansions would be performed, sometimes over 100 may be required. For a long thin conductive region, only a few expansions may be required.
FIG. 9 (compare FIG. 2) shows three junctions 902, 904, 906 (compare 212, 214, 216) disposed in the left-hand leg of the conductor region 302, and three junctions 912, 914, 916 (compare 212, 214, 216) disposed in the right-hand leg of the conductor region 302. The junctions 902, 904, 906 are all within the reachable area 810a of the conductor region 302. The junction 912 is within the reachable area 810b of the conductor region 302. The junction 914 is partially within the unreachable area 712, and the junction 914 is entirely within the unreachable region 712.
Although this approach to the problem has the advantage of simplicity, it has two drawbacks: (i) poor performance due to a large number of complex operations; and (ii) lack of accuracy due to the application of rectilinear expansion operations, which cause corners to expand faster than sides. The corner expansion problem is illustrated in FIG. 10. There, it can be seen that when the sides of a contact 1004 (compare 204) expand by a distance “D”, the corners expand by a distance equal to the square root of 2, or 1.41 times D—in other words, the corners expand 41% more than the sides. This can lead to erroneous results. This “corner error” could theoretically be mitigated by rounding the corners, but this would result in a major additional performance penalty, particularly when working with vector representations of shapes.